Announcements

• July 16, 2012 (Mon):
  Released the TAU 2012 contest presentation with results. Please look under the Contest Benchmarks and Results section.
• Nov 23, 2011: Released ibmpg2t on TAMU website.
• Nov 22, 2011: Extended the final code submission deadline.
• Oct 23, 2011: Uploaded new ibmpg1t solution file. There are some errors in previous one (the voltages at certain nodes and certain time points are not accurate). Thanks Xuanxing for the help to find the bug.
• Sep 30, 2011: Extended the Alpha code submission deadline and basic machine information.
• Aug 30, 2011: Extended the registration deadline.
• July 13, 2011: Announcement of 2012 Contest.
  
  First, we would like to thank all the participants in the 2011 TAU Power Grid Simulation Contest . We have decided to have a second power grid simulation contest in 2012. In the 2011 contest, we asked each team to perform a DC solution for a given power grid network, and the evaluation was based on accuracy, memory and speed on a single-core machine. This year, the focus will be on transient solution and parallel implementation. More details will be released very soon.
  
  This year the contest will be administrated by Raju Balasubramanian, Frank Liu and Zhuo Li from IBM. Please send all emails regarding to the contest to taucontest2011@gmail.com (Please add TAU2012_contest to your subject line for any emails regarding the contest.)
  
  To be considered for the contest, you must register by Sep 1, 2011 by sending an email to the email address above. This will enable the administrator to create a targeted mailing list to email relevant contest information. Please include the following information in your registration:
  
  
  • Name of your power grid simulator
  • Names of the developers
  • Affiliation of the team/contestant
  • One email id as the corresponding member of the team
  
  Please read the website "Benchmark_Format" under Benchmark Format. This has important information regarding the benchmark format.
  

Contest Benchmarks and Results

1. Test benchmarks: ibmpg1t and ibmpg2t from this site.
2. Final benchmarks will be released after the contest.
3. TAU 2012 Contest Presentation with Results.

Contact Information

• This year the contest will be administered by Raju Balasubramanian, Zhuo Li and Frank Liu from IBM. Please send all emails regarding the contest to taucontest2011@gmail.com.
• Please add "TAU2012_Contest" to your subject line.

Schedule

Submission Information

1. Please name your binary as your solver name. We do not want to have 5 "solver" and 5 "main" binaries.
2. You do not need to print extra information if that takes runtime. All we need is the solution file and we will count the runtime ourself.
3. If you have any special performance tuning parms, please remove them or hardcode inside your program. For the contest, we only take two options, one is for input file and one is for output file.
4. Please provide an arg to your program so that I can specify the solution file name.
5. Please try to submit a statically-linked binary as it helps with portability. (use gcc -static).
6. Each team is allowed to submit a single binary that should run on all the benchmarks.
7. We encourage the participants to explore parallel implementations of the simulation algorithms. Our machine has 32 cores, 64 threads and supports OpenMP. Note that we do not restricts with OpenMP implementation though.
8. No precomputed information can be used to influence the current run. The run directories will be cleaned prior to each run.
9. Purpose of alpha (preliminary) binary submission:
   The purpose of the alpha binary submission is: (a) to verify that I can run your binary on the contest machine. (b) to test that your binary is able to produce required formats on the test benchmarks.
10. Memory limit per job: 700GB RAM, 300GB swap memory
11. Machine configuration for the contest:
    • OS: Red Hat Enterprise Linux Server release 5.6 (Tikanga)
    • CPU: 64-bit Intel(R) Xeon(R) CPU X7560 @ 2.27GHz
    • GCC version: gcc version 4.1.2 20080704 (Red Hat 4.1.2-50)
      Thread model: posix Target: x86_64-redhat-linux
    • BLAS: versio 3.0, release 37.e15. lapack version 3.0, release 37.e15
    • Tcl: 8.4.13, release 4.e15
    • Information from /proc/cpuinfo:

      processor	: 0
      vendor_id	: GenuineIntel
      cpu family	: 6
      model		: 46
      model name	: Intel(R) Xeon(R) CPU           X7560  @ 2.27GHz
      stepping	: 6
      cpu MHz		: 1064.000
      cache size	: 24576 KB
      physical id	: 0
      siblings	: 16
      core id		: 0
      cpu cores	: 8
      apicid		: 0
      fpu		: yes
      fpu_exception	: yes
      cpuid level	: 11
      wp		: yes
      flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx rdtscp lm constant_tsc ida nonstop_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr sse4_1 sse4_2 popcnt lahf_lm
      bogomips	: 4522.16
      clflush size	: 64
      cache_alignment	: 64
      address sizes	: 44 bits physical, 48 bits virtual
      power management: [8]
      
      
      processor	: 63
      vendor_id	: GenuineIntel
      cpu family	: 6
      model		: 46
      model name	: Intel(R) Xeon(R) CPU           X7560  @ 2.27GHz
      stepping	: 6
      cpu MHz		: 1064.000
      cache size	: 24576 KB
      physical id	: 3
      siblings	: 16
      core id		: 11
      cpu cores	: 8
      apicid		: 119
      fpu		: yes
      fpu_exception	: yes
      cpuid level	: 11
      wp		: yes
      flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx rdtscp lm constant_tsc ida nonstop_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr sse4_1 sse4_2 popcnt lahf_lm
      bogomips	: 4522.07
      clflush size	: 64
      cache_alignment	: 64
      address sizes	: 44 bits physical, 48 bits virtual
      power management: [8]
        

Evaluation and Ranking

• The metrics for evaluation will be based on four categories
  • CPU;
  • Memory;
  • Maximum absolute error of the voltages among all time points and nodes.
  • Average absolute error of the voltages among all time points and nodes.
  
  For each team, their power grid simulator will be run on all benchmarks. For each benchmark, a score is given in each category according to the simulation results, and the sum of the scores of all categories is the score for this benchmark. The final score of each team is the sum of the scores of all benchmarks. Here are some additional information for the score function in each category.
  • CPU: The CPU score is from 0 to 100. It will be computed by normalizing the runtime of the the submitted simulator to the runtime of "an internal solver" (with reasonable scaling).
  • Memory: The Memory score is from 0 to 100. It will be computed by normalizing the memory of the the submitted simulator to the memory of "an internal solver" (with reasonable scaling).
  • Maximum absolute error: The score is from 0 to 100. If the maximum absolute error is less than 1 mV, the score is 0. If the max absolute error is larger than 10 mV, the score is 100.
  • Average absolute error: The score is from 0 to 100. If the average absolute error is less than 0.1 mV, the score is 0. If the average absolute error is larger than 1 mV, the score is 100.
  • If your simulator runs out of memory for a benchmark, it gets 400 score for this benchmark automatically.

Utility Scripts

• None.

Frequently Asked Questions

Benchmark Format

Participating Teams

• Coming soon.

Call for Participation