Thursday, May 1st, 2025

Session on Glitches, Soft errors, and Asynchronous Circuits

• UPSET: SET Analysis and Optimization Flow for VLSI circuits based on Static Timing Analysis and Closed-loop IN-place Optimizations , Christos Sotiriou (Invited).
• In-Place Timing Optimisation Tool Flow for Asynchronous Circuits, Dimitrios Tsalapatas, Nikolaos Chatzivangelis, Christos P. Sotiriou and Nikolaos Sketopoulos.
• Fast and Accurate Glitch Propagation Modeling Using ANNs, Anastasis Vagenas, Dimitrios Garyfallou and George Stamoulis.

Session on Sensitivity Libraries

• Get rid of nonsens from optimization and analysis, Chirayu Amin (Invited)
• Panel on sensitivity libraries (in planning).

Session on Cryogenic Computing

• Cryogenic Computing, Michihiro Shintani (Invited, placeholder title)
• Compact Modeling for Cryogenic-aware Forward Body Biasing in 180nm Bulk CMOS, Zhipeng Liang, Shin Taniguchi, Hajime Takayama and Michihiro Shintani.
• Ternary Logic Operation of CMOS Inverters under Low-temperature and Low-voltage Conditions, Kotaro Tominaga, Ryosuke Matsuo, Yoshihiro Midoh, Noriyuki Miura, Michihiro Shintani and Jun Shiomi.

Session on IR-induced Delay

• IR-induced rail waveforms and their impact on timing, Ahmed Shebaita and Qian Shen (Invited, placeholder title)
• Analysis and Mitigation of IR-drop Induced Delay Effects Using Machine Learning, Megha Srinivas, Raj Shah, Omar Yamak, Ahmed Shebaita and Hamid Mahmoodi.

Friday, May 2nd, 2025

• Keynote: Timing in Biological Neural Systems, Louis Scheffer.
• Resource saving opportunities from standardization of holistic timing sign-off for energy-efficient Cloud silicon with Adaptive Voltage Scaling, Christian Lutkemeyer (Co-chair).
• Panel on AVS (In planning).
• Future of Tau, Paul Pereira, Christian Lutkemeyer, Ahmed Shebaita.

Important dates

• Paper submission deadline: Feb 11, 2025 (Monday)
• Acceptance notification: Feb 24, 2025 (Monday)
• Final paper submission: Mar 1, 2025 (Saturday)

It has become clear that timing analysis is NO longer a solved problem. So, what are new challenges as the industry embraces 5/3/2nm and below, rides the wave of ultra-low-power mobile, wearable devices and jumps on the IoT bandwagon? Are there new issues with older nodes, 14/28nm and up, in new design use cases? How do we model timing/power interactions? How do reliability requirements coming from ADAS/IoT and related impact timing? How to we apply AI/ML/Data Science techniques to the timing domain? How do we meet the insatiable demands for accuracy, performance and functionality? What new fundamental challenges are coming from process physics, 3D, variability, voltage sensitivity, analog effects, Quantum circuit modeling, Ising Models, Mixed signal modeling and validation?

It has become clear that timing analysis is NO longer a solved problem. So, what are new challenges as the industry embraces 5/3/2nm and below, rides the wave of ultra-low-power mobile, wearable devices and jumps on the IoT bandwagon? Are there new issues with older nodes, 14/28nm and up, in new design use cases? How do we model timing/power interactions? How do reliability requirements coming from ADAS/IoT and related impact timing? How to we apply AI/ML/Data Science techniques to the timing domain? How do we meet the insatiable demands for accuracy, performance and functionality? What new fundamental challenges are coming from process physics, 3D, variability, voltage sensitivity, analog effects, Quantum circuit modeling, Ising Models, Mixed signal modeling and validation?